Embodiments of the present invention relate generally to a method and apparatus for generating clock signals in a high-speed digital transceiver, and more particularly to generating a second clock signal from a first clock signal.
High-speed digital communication networks over copper and optical fiber are used in many network communication and digital storage applications. Ethernet and Fibre Channel are two widely used communication protocols used today and continue to evolve to respond to the increasing need for higher bandwidth in digital communication systems.
The Open Systems Interconnection (OSI) model (ISO standard) was developed to establish standardization for linking heterogeneous computer and communication systems. The OSI model includes seven distinct functional layers including Layer 7: an application layer; Layer 6: a presentation layer; Layer 5: a session layer; Layer 4: a transport layer; Layer 3: a network layer; Layer 2: a data link layer; and Layer 1: a physical layer. Each OSI layer is responsible for establishing what is to be done at that layer of the network but not how to implement it.
Layers 1 to 4 handle network control and data transmission and reception. Layers 5 to 7 handle application issues. Specific functions of each layer may vary to a certain extent, depending on the exact requirements of a given protocol to be implemented for the layer. For example, the Ethernet protocol provides collision detection and carrier sensing in the data link layer.
The physical layer, Layer 1, is responsible for handling all electrical, optical, and mechanical requirements for interfacing to the communication media. The physical layer provides encoding and decoding, synchronization, clock data recovery, and transmission and reception of bit streams. Typically, high-speed electrical or optical transceivers are the hardware elements used to implement this layer.
As data rate and bandwidth requirements increase, 10 Gigabit data transmission rates are being developed and implemented in high-speed networks. There is much pressure to develop a 10 Gigabit physical layer for high-speed serial data applications.
In the physical layer, several sublayers are supported. As an example, for 10 Gigabit serial operation, some of the key sublayers include a PMD TX/RX (physical media dependent transmit and receive) sublayer, a PMD PCS (physical media dependent physical encoding) sublayer, a XGXS PCS (10 Gigabit media independent interface extender physical encoding) sublayer, and a XAUI TX/RX (10 Gigabit attachment unit interface transmit and receive) sublayer.
An optical-based transceiver, for example, includes various functional components such as clock data recovery, clock multiplication, serialization/de-serialization, encoding/decoding, electrical/optical conversion, descrambling, controlling, and data storage.
Certain functional components within an optical-based transceiver may require clock signals having slightly different effective clock frequencies. For example, a clock data recovery (CDR) circuit and a synchronizer/descrambler/decoder circuit may require slightly different effective clock frequencies in an optical-based transceiver. Typically, the clock signals are generated independently of each other, or one clock signal is multiplied up and then divided down by large ratios to achieve a second clock signal. Such methods require significant additional hardware than that required for generating a single original clock signal.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.